The present invention relates to improved current biasing of integrated injection logic (I.sup.2 L) circuits.
I.sup.2 L circuits are formed in an integrated circuit and comprise an inverted npn transistor structure having multiple open collectors and an pnp injector, as is well known. The collector of the pnp injector is formed in common with the base input of the npn transistor while its base is common to the emitter of the latter. Biasing of the I.sup.2 L circuit is normally achieved by connecting a resistor from the emitter of the injector to a positive voltage. This technique though very simple, has the drawback that the hole efficiency of the injector alpha determines the amount current sourced from the injector to the base of the inverted npn transistor. This current then directly effects the charging of the input node (base of the npn transistor) of the I.sup.2 L circuit and is dependent on process variations in the manufacturing of the integrated circuit. Hence, the speed of operation of the I.sup.2 L circuit will vary with process tolerances in production of such circuits. This is undesirable in that the circuit can fail circuit specifications which reduces yield of production parts incorporating such I.sup.2 L circuits.
Thus, there is a need for an improved biasing arrangement for use in I.sup.2 L circuits for minimizing the effects of injector alpha on the speed of the circuit due to integrated circuit fabrication process tolerances.